Submicron BiCMOS technologies for supercomputer and high speed system implementation

This paper describes submicron process technologies that allow a full implementation of CPU, first level Cache, second level Cache, and the main memory in a BiCMOS approach. CPU Standard Cells up to l00K ECL gate density with embedded CMOS and BiCMOS SRAM, X9 Cache memories, and 1 Meg ECL U0 SRAMs with less than 7ns access time are achieved. INTRODUCTION State-of-the-art BiCMOS technologies are vital tools of today's manufacturing and as such they are being extensively used to realize high performance semiconductor products while maintaining high density at moderate power consumption. Due to extra processing steps, cost per wafer for BiCMOS processes is higher than pure CMOS or Bipolar technologies. However, due to performance and density improvement BiCMOS processes enjoy lower cost per gate than ECL at a lower power level, comparable to CMOS products. For memory products BICMOS processes offer higher speed performance along with TTL and ECL I/O options. Using BiCMOS processes tailored for ASIC applications, on the other hand, memory arrays can be incorporated into existing or new designs adding to product versatility and leading to increased performance for systems employing such products. In this paper two major BiCMOS technology families are discussed and compared in terms of processing and device performance. In addition areas of application for each one of these processes as related to the total system solution will be explored. ASIC & MEMORY BICMOS FAMILIES Currently two major high performance BiCMOS technology families exist in National Semiconductors. A technology road map for these process families is shown in TABLE-I. Advanced BiCMOS process family, known as ABiC, is the family of BiCMOS technologies developed for high performance ASIC applications with emphasis on embedded CMOS, BiCMOS or ECL memory as well as BiCMOS and ECL gate array and standard cells. In development of ABiC process, National Semiconductor's state-of-the-art ASPECT process [ 1,2], has been successfully combined with high performance CMOS process [3,4,5]. The second technology family, known as BiCMOS, is mainly developed for SRAM applications where dense 4T MOS memory cells combined with high speed bipolar logic leads to very high levels of device integration. Final bipolar and CMOS device cross sections for current generation of the ABiC family, ABiC IV, are shown in Fig.1. In Fig.2 process cross section for the 0.8 pm BiCMOS IV technology [6,7] is shown. Despite differences in architecture a high degree of similarity and synergy exists between these processes. Device isolation in both processes is accomplished using an advanced, low encroachment fully recessed oxide isolation process optimized for small birds beak and planarity as well as defect density. The N+ and P+ twin buried layers form retrograde well profiles for CMOS transistors and result in soft error and latch up immunity. The gate oxide is 150 A thick and in the ABiC IV process is protected by a thin layer of polysilicon during subsequent masWetch process. The major difference between technologies is in the use of the polysilicon 1ayers.As shown in Fig.1, in the ABiC IV a single layer of polysilicon is used for simultaneous formation of gate, emitter, sourceldrain and base contacts as well as several high precision poly resistors. The same layer of polysilicon is silicided and used for local interconnection, increasing design flexibility and packing density. The BiCMOS IV process on the other hand is a double poly technology where the first poly layer forms the gate of the CMOS devices. The second poly layer foms emitter of bipolar transistors as well as high value load resistors for high density 4T cell memory implementation. The area of memory cell in BiCMOS IV is about 37 pm2. The second layer of poly is also selectively silicided, facilitating the formation of low-resistance local interconnects leading to smaller memory foot print and pitch. In contrast, 6T memory cells are more appropriate in ABiC IV where a larger memoxy cell area of about 100 pm2 can be tolerated. Other key features for these technologies are summarized in TABLE-II. ELECTRICAL PERFORMANCE Key device electrical parameters are summarized in TABLE-III. Both technologies enjoy respectable Idsat of 0.4 mA/pm for NMOS and 0.2 mA/pm for PMOS devices and for nominal effective channel length of 0.6 pm. Unity gain frequency, Ft, is about 15 GHz for bipolar transistors. ABiC IV devices , however, have lower extrinsic base resistance as well as S/D resistance due to self aligned silicide. Smaller bipolar foot print in ABiC IV leads to reduced device capacitance as shown in TABLE-111. Gate delay information for ABiC IV and BiCMOS IV are summarized in TABLE-IV. From TABLE-IV both technologies offer similar high performance for CMOS and BiCMOS gates. Delay x power products for several high performance technologies including ABiC IV and BiCMOS IV is given in Fig.3 .ECL performance in ABiC IV technology is superior due to highly optimized bipolar architecture and with gate delay of about 200 psec at 50 pA of current, high levels of integration can be achieved.ABiC IV also offers optimal interconnection performance of less than 1 pS/mil ( 40 pS/mm) for 4 layers of interconnection. CH2909-019010000/0007$01 .OO